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VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 233kb
Downloaded :0次
Author :
刘***
About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Reedit
Detailed design of asynchronous fifo Gray code in the address of the code in effect and the emergence of Man flag
Packet file list
(Preview for download)
D触发器.mht
Gray code原理_veriolg代码实现.mht
Verilog编码规范.mht
异步FIFO及verilog原码_1.mht
异步FIFO及verilog原码_2.mht
状态机写法总结非index与index写法.mht
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