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LPM_ROMsin_signal_generator(12×256)MAX502

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 255kb
  • Downloaded :0次
  • Author :刘***
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Introduction - If you have any usage issues, please Google them yourself
Based on 12 of the MAX502 chip DAC chips in parallel procedures, the use of FPGA in the ROM look-up table for data storage
Packet file list
(Preview for download)
data_rom.bsf
data_rom.cmp
data_rom.vhd
db
..\altsyncram_9b51.tdf
..\sin12.analyze_file.qmsg
..\sin12.asm.qmsg
..\sin12.cbx.xml
..\sin12.cmp.cdb
..\sin12.cmp.hdb
..\sin12.cmp.kpt
..\sin12.cmp.logdb
..\sin12.cmp.rdb
..\sin12.cmp.tdb
..\sin12.cmp0.ddb
..\sin12.dbp
..\sin12.db_info
..\sin12.eco.cdb
..\sin12.fit.qmsg
..\sin12.hier_info
..\sin12.hif
..\sin12.map.cdb
..\sin12.map.hdb
..\sin12.map.logdb
..\sin12.map.qmsg
..\sin12.pre_map.cdb
..\sin12.pre_map.hdb
..\sin12.psp
..\sin12.rtlv.hdb
..\sin12.rtlv_sg.cdb
..\sin12.rtlv_sg_swap.cdb
..\sin12.sgdiff.cdb
..\sin12.sgdiff.hdb
..\sin12.signalprobe.cdb
..\sin12.sld_design_entry.sci
..\sin12.sld_design_entry_dsc.sci
..\sin12.syn_hier_info
..\sin12.tan.qmsg
frediv.vhd
freqdiv.bsf
romgen.c
romgen.exe
sin12.asm.rpt
sin12.bdf
sin12.cdf
sin12.done
sin12.dpf
sin12.fit.rpt
sin12.fit.smsg
sin12.fit.summary
sin12.flow.rpt
sin12.map.rpt
sin12.map.summary
sin12.mif
sin12.pin
sin12.pof
sin12.qpf
sin12.qsf
sin12.qws
sin12.sof
sin12.tan.rpt
sin12.tan.summary
sinn.bsf
sinn.vhd
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