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Reference_Design

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.64mb
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Introduction - If you have any usage issues, please Google them yourself
University plans altera package, including basic configuration, can be directly transplanted
Packet file list
(Preview for download)
Reference_Design
................\DE2_NIOS
................\........\altpllpll_0.ppf
................\........\Audio_0.v
................\........\Audio_DAC_FIFO
................\........\..............\cb_generator.pl
................\........\..............\class.ptf
................\........\..............\hdl
................\........\..............\...\AUDIO_DAC_FIFO.v
................\........\..............\...\FIFO_16_256.v
................\........\AUDIO_DAC_FIFO.v
................\........\Audio_PLL.ppf
................\........\Audio_PLL.v
................\........\bht_ram.mif
................\........\Binary_VGA_Controller
................\........\.....................\cb_generator.pl
................\........\.....................\class.ptf
................\........\.....................\hdl
................\........\.....................\...\Img_DATA.hex
................\........\.....................\...\Img_RAM.v
................\........\.....................\...\VGA_Controller.v
................\........\.....................\...\VGA_NIOS_CTRL.v
................\........\.....................\...\VGA_OSD_RAM.v
................\........\.....................\...\VGA_Param.h
................\........\.....................\inc
................\........\.....................\...\VGA.c
................\........\.....................\...\VGA.h
................\........\button_pio.v
................\........\clock_0.v
................\........\clock_1.v
................\........\cmp_state.ini
................\........\cpu_0.ocp
................\........\cpu_0.v
................\........\cpu_0.vo
................\........\cpu_0_bht_ram.mif
................\........\cpu_0_dc_tag_ram.mif
................\........\cpu_0_ic_tag_ram.mif
................\........\cpu_0_jtag_debug_module.v
................\........\cpu_0_jtag_debug_module_wrapper.v
................\........\cpu_0_mult_cell.v
................\........\cpu_0_ociram_default_contents.mif
................\........\cpu_0_rf_ram_a.mif
................\........\cpu_0_rf_ram_b.mif
................\........\cpu_0_test_bench.v
................\........\dc_tag_ram.mif
................\........\DE2_Board
................\........\.........\class.ptf
................\........\.........\system
................\........\.........\......\asmi.v
................\........\.........\......\cmp_state.ini
................\........\.........\......\cpu_0.ocp
................\........\.........\......\cpu_0.v
................\........\.........\......\cpu_0_test_bench.v
................\........\.........\......\data_RAM.hex
................\........\.........\......\data_RAM.v
................\........\.........\......\DE2_Board.asm.rpt
................\........\.........\......\DE2_Board.bsf
................\........\.........\......\DE2_Board.cdf
................\........\.........\......\DE2_Board.done
................\........\.........\......\DE2_Board.fit.eqn
................\........\.........\......\DE2_Board.fit.rpt
................\........\.........\......\DE2_Board.fit.summary
................\........\.........\......\DE2_Board.flow.rpt
................\........\.........\......\DE2_Board.map.eqn
................\........\.........\......\DE2_Board.map.rpt
................\........\.........\......\DE2_Board.map.summary
................\........\.........\......\DE2_Board.pin
................\........\.........\......\DE2_Board.pof
................\........\.........\......\DE2_Board.ptf
................\........\.........\......\DE2_Board.ptf.5.00
................\........\.........\......\DE2_Board.ptf.bak
................\........\.........\......\DE2_Board.qpf
................\........\.........\......\DE2_Board.qsf
................\........\.........\......\DE2_Board.qws
................\........\.........\......\DE2_Board.sof
................\........\.........\......\DE2_Board.tan.rpt
................\........\.........\......\DE2_Board.tan.summary
................\........\.........\......\DE2_Board.v
................\........\.........\......\DE2_Boar
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