VHDL realize I2C interface SPI interface to the source code, you can directly call

an486_design_example
....................\AN486_SPI_to_I2C_Altera_MAX_II_CPLD_Design_Example
....................\..................................................\code
....................\..................................................\....\SPI_to_I2C.v
....................\..................................................\modelsim
....................\..................................................\........\SPI_to_I2C.cr.mti
....................\..................................................\........\SPI_to_I2C.mpf
....................\..................................................\........\SPI_to_I2C.v
....................\..................................................\........\SPI_to_I2C_test.v
....................\..................................................\........\SPI_to_I2C_test.v.bak
....................\..................................................\........\transcript
....................\..................................................\........\vsim.wlf

....................\..................................................\........\wave.do
....................\..................................................\........\work
....................\..................................................\........\....\@i2@c_master
....................\..................................................\........\....\............\verilog.psm
....................\..................................................\........\....\............\_primary.dat
....................\..................................................\........\....\............\_primary.vhd
....................\..................................................\........\....\@s@p@i_slave
....................\..................................................\........\....\............\verilog.psm
....................\..................................................\........\....\............\_primary.dat
....................\..................................................\........\....\............\_primary.vhd
....................\..................................................\........\....\@s@p@i_to_@i2@c
....................\..................................................\........\....\...............\verilog.psm
....................\..................................................\........\....\...............\_primary.dat
....................\..................................................\........\....\...............\_primary.vhd
....................\..................................................\........\....\@s@p@i_to_@i2@c_test
....................\..................................................\........\....\....................\verilog.psm
....................\..................................................\........\....\....................\_primary.dat
....................\..................................................\........\....\....................\_primary.vhd
....................\..................................................\........\....\divider
....................\..................................................\........\....\.......\verilog.psm
....................\..................................................\........\....\.......\_primary.dat
....................\..................................................\........\....\.......\_primary.vhd
....................\..................................................\........\....\internal_oss_altufm_osc_7p3
....................\..................................................\........\....\...........................\verilog.psm
....................\..................................................\........\....\...........................\_primary.dat
....................\..................................................\........\....\...........................\_primary.vhd
....................\..................................................\........\....\_info
....................\..................................................\quartus
....................\.........................

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