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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 152kb
  • Downloaded :0次
  • Author :李***
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Introduction - If you have any usage issues, please Google them yourself
Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.01. Realize this instance through the ModelSim tool realize a
Packet file list
(Preview for download)
paobiao
.......\project
.......\.......\.untf
.......\.......\automake.log
.......\.......\bitgen.ut
.......\.......\paobiao.bgn
.......\.......\paobiao.bit
.......\.......\paobiao.bld
.......\.......\paobiao.cmd_log
.......\.......\paobiao.dhp
.......\.......\paobiao.drc
.......\.......\paobiao.ise
.......\.......\paobiao.ise_ISE_Backup
.......\.......\paobiao.lso
.......\.......\paobiao.mrp
.......\.......\paobiao.nc1
.......\.......\paobiao.ncd
.......\.......\paobiao.ngc
.......\.......\paobiao.ngd
.......\.......\paobiao.ngm
.......\.......\paobiao.ngr
.......\.......\paobiao.pad
.......\.......\paobiao.pad_txt
.......\.......\paobiao.par
.......\.......\paobiao.pcf
.......\.......\paobiao.placed_ncd_tracker
.......\.......\paobiao.prj
.......\.......\paobiao.routed_ncd_tracker
.......\.......\paobiao.stx
.......\.......\paobiao.syr
.......\.......\paobiao.twr
.......\.......\paobiao.twx
.......\.......\paobiao.ut
.......\.......\paobiao.v
.......\.......\paobiao.xpi
.......\.......\paobiao_last_par.ncd
.......\.......\paobiao_map.ncd
.......\.......\paobiao_map.ngm
.......\.......\paobiao_pad.csv
.......\.......\paobiao_pad.txt
.......\.......\paobiao_summary.html
.......\.......\paobiao_tb.ant
.......\.......\paobiao_tb.fdo
.......\.......\paobiao_tb.jhd
.......\.......\paobiao_tb.tbw
.......\.......\paobiao_tb.tfw
.......\.......\paobiao_tb.udo
.......\.......\paobiao_tb.xwv
.......\.......\paobiao_tb.xwv_bak
.......\.......\paobiao_tb_bencher.prj
.......\.......\paobiao_tb_tb.v
.......\.......\paobiao_tb_tb.v.bak
.......\.......\paobiao_vhdl.prj
.......\.......\transcript
.......\.......\vsim.wlf
.......\.......\work
.......\.......\....\glbl
.......\.......\....\....\verilog.asm
.......\.......\....\....\_primary.dat
.......\.......\....\....\_primary.vhd
.......\.......\....\paobiao
.......\.......\....\.......\verilog.asm
.......\.......\....\.......\_primary.dat
.......\.......\....\.......\_primary.vhd
.......\.......\....\paobiao_tb
.......\.......\....\..........\verilog.asm
.......\.......\....\..........\_primary.dat
.......\.......\....\..........\_primary.vhd
.......\.......\....\_info
.......\.......\xst
.......\.......\...\dump.xst
.......\.......\...\........\paobiao.prj
.......\.......\...\........\...........\ngx
.......\.......\...\........\...........\...\notopt
.......\.......\...\........\...........\...\opt
.......\.......\...\work
.......\.......\...\....\hdllib.ref
.......\.......\...\....\vlg73
.......\.......\...\....\.....\paobiao.bin
.......\.......\_ngo
.......\.......\....\netlist.lst
.......\.......\_xmsgs
.......\.......\__projnav
.......\.......\.........\bitgen.rsp
.......\.......\.........\ednTOngd_tcl.rsp
.......\.......\.........\nc1TOncd_tcl.rsp
.......\.......\.........\paobiao.gfl
.......\.......\.........\paobiao.xst
.......\.......\.........\paobiao_flowplus.gfl
.......\.......\.........\paobiao_ncdTOut_tcl.rsp
.......\.......\.........\runXst_tcl.rsp
.......\.......\.........\sumrpt_tcl.rsp
.......\.......\__projnav.log
.......\rtl
.......\...\paobiao.v
.......\...\paobiao_tb.tbw
.......\说明.txt
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