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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 5.1mb
  • Downloaded :0次
  • Author :willi*****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
VHDL subprogram, including a variety of routine information as well as the source.
Packet file list
(Preview for download)
VHDL_CD
.......\BOOK1
.......\.....\ADDER1
.......\.....\......\ADDER1
.......\.....\......\......\adder1
.......\.....\......\......\......\adder1.exp
.......\.....\......\......\......\chips
.......\.....\......\......\......\.....\ver1
.......\.....\......\......\......\.....\....\ver1.cst
.......\.....\......\......\......\.....\....\ver1.rpt
.......\.....\......\......\......\.....\....\ver1.ws
.......\.....\......\......\......\.....\ver1-Optimized
.......\.....\......\......\......\.....\..............\ver1-Optimized.cst
.......\.....\......\......\......\.....\..............\ver1-Optimized.rpt
.......\.....\......\......\......\.....\..............\ver1-Optimized.ws
.......\.....\......\......\......\files
.......\.....\......\......\......\.....\L0.rpt
.......\.....\......\......\......\workdirs
.......\.....\......\......\......\........\WORK
.......\.....\......\......\......\........\....\ADDER1.hnl
.......\.....\......\......\......\........\....\ADDER1.mra
.......\.....\......\......\......\........\....\ADDER1.out
.......\.....\......\......\......\........\....\ADDER1.sim
.......\.....\......\......\......\........\....\ADDER1.sts
.......\.....\......\......\......\........\....\ADDER1.syn
.......\.....\......\......\......\........\....\ADDER1__ADDER1_ARCH.sim
.......\.....\......\......\......\........\....\ADDER1__ADDER1_ARCH.syn
.......\.....\......\......\......\........\....\Anal.info
.......\.....\......\......\......\........\....\Anal.out
.......\.....\......\......\adder1.alb
.......\.....\......\......\adder1.bak
.......\.....\......\......\ADDER1.CMD
.......\.....\......\......\adder1.EDF
.......\.....\......\......\adder1.er
.......\.....\......\......\adder1.log
.......\.....\......\......\adder1.prj
.......\.....\......\......\ADDER1.TVE
.......\.....\......\......\adder1.ucf
.......\.....\......\......\adder1.vhd
.......\.....\......\......\dpm_net
.......\.....\......\......\.......\ADDER1.edf
.......\.....\......\......\ERRLOG.LOG
.......\.....\......\......\express.ini
.......\.....\......\......\lib
.......\.....\......\......\...\ADDER1.BLK
.......\.....\......\......\...\ADDER1.DIR
.......\.....\......\......\...\ADDER1.FIG
.......\.....\......\......\...\ADDER1.FLG
.......\.....\......\......\...\ADDER1.GNR
.......\.....\......\......\...\ADDER1.HDR
.......\.....\......\......\...\ADDER1.ID
.......\.....\......\......\...\ADDER1.INI
.......\.....\......\......\...\ADDER1.MAP
.......\.....\......\......\...\ADDER1.MOD
.......\.....\......\......\...\ADDER1.PIN
.......\.....\......\......\...\ADDER1.SYM
.......\.....\......\......\...\ADDER1.SYN
.......\.....\......\......\...\ADDER1.VIS
.......\.....\......\......\logiblox.ini
.......\.....\......\......\NETLIST.LOG
.......\.....\......\......\S95.log
.......\.....\......\......\xproj
.......\.....\......\......\.....\adder1.xpj
.......\.....\......\......\.....\ver1
.......\.....\......\......\.....\....\version.vbf
.......\.....\......\......\xproj.ini
.......\.....\......\......\~~HIER~~.IDX
.......\.....\......\ADDER1.txt
.......\.....\......\S95.log
.......\.....\ALIAS1
.......\.....\......\ALIAS1
.......\.....\......\......\alias1
.......\.....\......\......\......\alias1.exp
.......\.....\......\......\......\chips
.......\.....\......\......\......\.....\ver1
.......\.....\......\......\......\.....\....\ver1.cst
.......\.....\......\......\......\.....\....\ver1.rpt
.......\.....\......\......\......\.....\....\ver1.ws
.......\.....\......\......\......\.....\ver1-Optimized
.......\.....\......\......\......\.....\..............\ver1-Optimized.cst
.......\.....\......\......\......\.....\..............\ver1-Optimized.rpt
.......\.....\......\......\......\.....\..............\ver1-Optimized.ws
.......\.....\......\......\......\files
.......\.....\......\......\......\.....\L1.rpt
.......\.....\......\......\......\.....\L2.rpt
.......\.....\......\......\......\workdirs
.......\.....\......\......\......\........\WORK
.......\.....\......\......\......\........\....\alias1.hnl
.......\.....\......\......\......\........\...
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