Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the

ADCtest
.......\cmp_state.ini
.......\db
.......\..\test.asm.qmsg
.......\..\test.cbx.xml
.......\..\test.cmp.cdb
.......\..\test.cmp.hdb
.......\..\test.cmp.rdb
.......\..\test.cmp.tdb
.......\..\test.cmp0.ddb
.......\..\test.db_info
.......\..\test.eco.cdb
.......\..\test.fit.qmsg
.......\..\test.hier_info
.......\..\test.hif
.......\..\test.map.cdb
.......\..\test.map.hdb
.......\..\test.map.qmsg
.......\..\test.pre_map.cdb
.......\..\test.pre_map.hdb
.......\..\test.psp
.......\..\test.rtlv.hdb
.......\..\test.rtlv_sg.cdb
.......\..\test.rtlv_sg_swap.cdb
.......\..\test.sgdiff.cdb
.......\..\test.sgdiff.hdb
.......\..\test.signalprobe.cdb
.......\..\test.sld_design_entry.sci
.......\..\test.sld_design_entry_dsc.sci
.......\..\test.syn_hier_info
.......\..\test.tan.qmsg
.......\..\test_cmp.qrpt
.......\M10MHz.bsf
.......\M10MHz.vhd
.......\SetData.bsf
.......\SetData.vhd
.......\test.asm.rpt
.......\test.bdf
.......\test.cdf
.......\test.done
.......\test.fit.eqn
.......\test.fit.rpt
.......\test.fit.summary
.......\test.flow.rpt
.......\test.map.eqn
.......\test.map.rpt
.......\test.map.summary
.......\test.pin
.......\test.pof
.......\test.ppl
.......\test.qpf
.......\test.qsf
.......\test.qws
.......\test.sof
.......\test.tan.rpt
.......\test.tan.summary

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