FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available

asynch_fifo
...........\asynch_fifo
...........\...........\asyn_fifo.asm.rpt
...........\...........\asyn_fifo.done
...........\...........\asyn_fifo.eda.rpt
...........\...........\asyn_fifo.fit.rpt
...........\...........\asyn_fifo.fit.smsg
...........\...........\asyn_fifo.fit.summary
...........\...........\asyn_fifo.flow.rpt
...........\...........\asyn_fifo.map.rpt
...........\...........\asyn_fifo.map.smsg
...........\...........\asyn_fifo.map.summary
...........\...........\asyn_fifo.pin
...........\...........\asyn_fifo.pof
...........\...........\asyn_fifo.qpf
...........\...........\asyn_fifo.qsf
...........\...........\asyn_fifo.sim.rpt
...........\...........\asyn_fifo.sof
...........\...........\asyn_fifo.tan.rpt
...........\...........\asyn_fifo.tan.summary
...........\...........\asyn_fifo.v
...........\...........\asyn_fifo.v.bak
...........\...........\db
...........\...........\..\altsyncram_3nu.tdf
...........\...........\..\altsyncram_9ve1.tdf
...........\...........\..\altsyncram_ebc1.tdf
...........\...........\..\altsyncram_to61.tdf
...........\...........\..\alt_synch_pipe_1e8.tdf
...........\...........\..\alt_synch_pipe_kv7.tdf
...........\...........\..\alt_synch_pipe_lv7.tdf
...........\...........\..\alt_synch_pipe_tdb.tdf
...........\...........\..\asyn_fifo.asm.qmsg
...........\...........\..\asyn_fifo.asm_labs.ddb
...........\...........\..\asyn_fifo.cbx.xml
...........\...........\..\asyn_fifo.cmp.bpm
...........\...........\..\asyn_fifo.cmp.cdb
...........\...........\..\asyn_fifo.cmp.ecobp
...........\...........\..\asyn_fifo.cmp.hdb
...........\...........\..\asyn_fifo.cmp.logdb
...........\...........\..\asyn_fifo.cmp.rdb
...........\...........\..\asyn_fifo.cmp.tdb
...........\...........\..\asyn_fifo.cmp0.ddb
...........\...........\..\asyn_fifo.cmp2.ddb
...........\...........\..\asyn_fifo.db_info
...........\...........\..\asyn_fifo.eco.cdb
...........\...........\..\asyn_fifo.eda.qmsg
...........\...........\..\asyn_fifo.eds_overflow
...........\...........\..\asyn_fifo.fit.qmsg
...........\...........\..\asyn_fifo.hier_info
...........\...........\..\asyn_fifo.hif
...........\...........\..\asyn_fifo.map.bpm
...........\...........\..\asyn_fifo.map.cdb
...........\...........\..\asyn_fifo.map.ecobp
...........\...........\..\asyn_fifo.map.hdb
...........\...........\..\asyn_fifo.map.logdb
...........\...........\..\asyn_fifo.map.qmsg
...........\...........\..\asyn_fifo.map_bb.cdb
...........\...........\..\asyn_fifo.map_bb.hdb
...........\...........\..\asyn_fifo.map_bb.hdbx
...........\...........\..\asyn_fifo.map_bb.logdb
...........\...........\..\asyn_fifo.pre_map.cdb
...........\...........\..\asyn_fifo.pre_map.hdb
...........\...........\..\asyn_fifo.psp
...........\...........\..\asyn_fifo.root_partition.cmp.atm
...........\...........\..\asyn_fifo.root_partition.cmp.dfp
...........\...........\..\asyn_fifo.root_partition.cmp.hdbx
...........\...........\..\asyn_fifo.root_partition.cmp.logdb
...........\...........\..\asyn_fifo.root_partition.cmp.rcf
...........\...........\..\asyn_fifo.root_partition.map.atm
...........\...........\..\asyn_fifo.root_partition.map.hdbx
...........\...........\..\asyn_fifo.root_partition.map.info
...........\...........\..\asyn_fifo.rpp.qmsg
...........\...........\..\asyn_fifo.rtlv.hdb
...........\...........\..\asyn_fifo.rtlv_sg.cdb
...........\...........\..\asyn_fifo.rtlv_sg_swap.cdb
...........\...........\..\asyn_fifo.sgate.rvd
...........\...........\..\asyn_fifo.sgate_sm.rvd
...........\...........\..\asyn_fifo.sgdiff.cdb
...........\...........\..\asyn_fifo.sgdiff.hdb
...........\...........\..\asyn_fifo.signalprobe.cdb
...........\...........\..\asyn_fifo.sim.cvwf
...........\...........\..\asyn_fifo.sim.hdb
...........\...........\..\asyn_fifo.sim.qmsg
...........\...........\..\asyn_fifo.sim.rdb
...........\...........\..\asyn_fifo.sld_design_entry.sci
...........\...........\..\asyn_fifo.sld_design_entry_dsc.sci
...........\...........\..\asyn_fifo.smp_dump.txt
...........\...........\..\asyn_fifo.syn_hier_info
...........\

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．