Use of FPGA technology to achieve the pulse-width test, based on VHDL, test error of clock cycles

freq_cnt
........\db
........\..\freq_cnt.asm.qmsg
........\..\freq_cnt.cbx.xml
........\..\freq_cnt.cmp.cdb
........\..\freq_cnt.cmp.hdb
........\..\freq_cnt.cmp.kpt
........\..\freq_cnt.cmp.logdb
........\..\freq_cnt.cmp.rdb
........\..\freq_cnt.cmp.tdb
........\..\freq_cnt.cmp0.ddb
........\..\freq_cnt.cmp2.ddb
........\..\freq_cnt.dbp
........\..\freq_cnt.db_info
........\..\freq_cnt.eco.cdb
........\..\freq_cnt.eds_overflow
........\..\freq_cnt.fit.qmsg
........\..\freq_cnt.hier_info
........\..\freq_cnt.hif
........\..\freq_cnt.map.cdb
........\..\freq_cnt.map.hdb
........\..\freq_cnt.map.logdb
........\..\freq_cnt.map.qmsg
........\..\freq_cnt.pre_map.cdb
........\..\freq_cnt.pre_map.hdb
........\..\freq_cnt.psp
........\..\freq_cnt.rtlv.hdb
........\..\freq_cnt.rtlv_sg.cdb
........\..\freq_cnt.rtlv_sg_swap.cdb
........\..\freq_cnt.sgdiff.cdb
........\..\freq_cnt.sgdiff.hdb
........\..\freq_cnt.signalprobe.cdb
........\..\freq_cnt.sim.hdb
........\..\freq_cnt.sim.qmsg
........\..\freq_cnt.sim.rdb
........\..\freq_cnt.sim.vwf
........\..\freq_cnt.sim_ori.vwf
........\..\freq_cnt.sld_design_entry.sci
........\..\freq_cnt.sld_design_entry_dsc.sci
........\..\freq_cnt.syn_hier_info
........\..\freq_cnt.tan.qmsg
........\..\wed.zsf
........\freq_cnt.asm.rpt
........\freq_cnt.done
........\freq_cnt.fit.rpt
........\freq_cnt.fit.smsg
........\freq_cnt.fit.summary
........\freq_cnt.flow.rpt
........\freq_cnt.map.rpt
........\freq_cnt.map.summary
........\freq_cnt.pin
........\freq_cnt.qpf
........\freq_cnt.qsf
........\freq_cnt.qws
........\freq_cnt.sim.rpt
........\freq_cnt.tan.rpt
........\freq_cnt.tan.summary
........\freq_cnt.vhd
........\freq_cnt.vwf

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