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ModelSim
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VHDL-FPGA-Verilog
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Update : 2012-11-26
Size : 1.09mb
Downloaded :0次
Author :
邹****
About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Reedit
ModelSim using SystemC to do design verification methods and sample
Packet file list
(Preview for download)
modelsim
........\Debussy 仿真快速上手教程.doc
........\debussy和modelsim协同仿真.txt
........\ModelSim SE操作指南.txt
........\Modelsim 初学者心得.txt
........\Modelsim 包会教程.txt
........\ModelSim下用SystemC做设计验证方法与示例.txt
........\modelsim后仿真.doc
........\ModuleSim SE 快速入门.txt
........\使用说明请参看右侧注释====〉〉.txt
........\关于modelsim的使用.txt
........\利用ModelSim SE6.0C实现时序仿真.doc
........\如何仿真IP核(建立modelsim仿真库完整解析).doc
........\我的仿真工作流程.txt
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