Using VHDL language, on Altera s DE2 development board for development, which in this case the realization of paragraph 7 of the on-board digital tube display, in niosiiIDE hardware implementation based on a small circle of bright lights out

test
....\bin27seg.bsf
....\bin27seg.vhd
....\db
....\..\prev_cmp_seg7test.map.qmsg
....\..\seg7test.cbx.xml
....\..\seg7test.cmp.rdb
....\..\seg7test.dbp
....\..\seg7test.db_info
....\..\seg7test.eco.cdb
....\..\seg7test.hier_info
....\..\seg7test.hif
....\..\seg7test.map.bpm
....\..\seg7test.map.cdb
....\..\seg7test.map.ecobp
....\..\seg7test.map.hdb
....\..\seg7test.map.logdb
....\..\seg7test.map.qmsg
....\..\seg7test.map_bb.cdb
....\..\seg7test.map_bb.hdb
....\..\seg7test.map_bb.logdb
....\..\seg7test.pre_map.cdb
....\..\seg7test.pre_map.hdb
....\..\seg7test.psp
....\..\seg7test.pss
....\..\seg7test.rtlv.hdb
....\..\seg7test.rtlv_sg.cdb
....\..\seg7test.rtlv_sg_swap.cdb
....\..\seg7test.sgdiff.cdb
....\..\seg7test.sgdiff.hdb
....\..\seg7test.sld_design_entry.sci
....\..\seg7test.sld_design_entry_dsc.sci
....\..\seg7test.syn_hier_info
....\prev_cmp_seg7test.qmsg
....\seg7test.done
....\seg7test.flow.rpt
....\seg7test.map.rpt
....\seg7test.map.summary
....\seg7test.qpf
....\seg7test.qsf
....\seg7test.qws

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