With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.

cnt24.vhd
cnt60.vhd
fulladd.vhd
vote3.vhd
vote7.vhd

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