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viterbi_node_sync_design

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 268kb
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  • Author :d*****
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Introduction - If you have any usage issues, please Google them yourself
A complete viterbi decoding procedures and test procedures
Packet file list
(Preview for download)
altera
......\design_examples
......\...............\viterbi_node_sync
......\...............\.................\Quartus_II
......\...............\.................\..........\run_script.tcl
......\...............\.................\..........\viterbi_node_sync.qpf
......\...............\.................\..........\viterbi_node_sync.qsf
......\...............\.................\..........\wave.do
......\...............\.................\source
......\...............\.................\......\a_rcvsym.txt
......\...............\.................\......\a_txsym.txt
......\...............\.................\......\ber_node_sync.vhd
......\...............\.................\......\BER_report.txt
......\...............\.................\......\ber_threshold.vhd
......\...............\.................\......\block_period_stim.txt
......\...............\.................\......\mux_2d.vhd
......\...............\.................\......\rotate_node_sync.vhd
......\...............\.................\......\tcm_rcv_sector.txt
......\...............\.................\......\transbit.txt
......\...............\.................\......\viterbi_BER.bsf
......\...............\.................\......\viterbi_BER.cmp
......\...............\.................\......\viterbi_BER.html
......\...............\.................\......\viterbi_BER.inc
......\...............\.................\......\viterbi_BER.vhd
......\...............\.................\......\viterbi_BER.vho
......\...............\.................\......\viterbi_BER_bb.v
......\...............\.................\......\viterbi_BER_inst.vhd
......\...............\.................\......\viterbi_BER_logiclock_script.tcl
......\...............\.................\......\viterbi_BER_testbench.vhd
......\...............\.................\......\viterbi_BER_vital_script.tcl
......\...............\.................\......\viterbi_BER_vsim_script.tcl
......\...............\.................\......\viterbi_node_sync.vhd
......\...............\.................\testbench
......\...............\.................\.........\auk_vit_vit_var_enc_arc_rtl.vhd
......\...............\.................\.........\auk_vit_vit_var_enc_ent.vhd
......\...............\.................\.........\Bench_vit_par_atl_arc_ben_node_sync.vhd
......\...............\.................\.........\Bench_vit_par_atl_ent_node_sync.vhd
......\...............\.................\.........\viterbi_node_sync_testbench.vhd
......\...............\.................\.........\vi_bench.vhd
......\...............\.................\.........\vi_functions.vhd
......\...............\.................\.........\vi_interface.vhd
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