just division the clock into 2

clk
...\automake.log
...\clk.cmd_log
...\clk.dhp
...\clk.ise
...\clk.ise_ISE_Backup
...\clk.lso
...\clk.ngc
...\clk.ngr
...\clk.prj
...\clk.stx
...\clk.syr
...\clk.v
...\clk_summary.html
...\clk_test.v
...\clk_test_v.fdo
...\clk_test_v.udo
...\clk_vhdl.prj
...\transcript
...\vsim.wlf
...\work
...\....\clk
...\....\...\verilog.asm
...\....\...\_primary.dat
...\....\...\_primary.vhd
...\....\clk_test_v
...\....\..........\verilog.asm
...\....\..........\_primary.dat
...\....\..........\_primary.vhd
...\....\glbl
...\....\....\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\_info
...\xst
...\...\dump.xst
...\...\........\clk.prj
...\...\........\.......\ngx
...\...\........\.......\...\notopt
...\...\........\.......\...\opt
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg32
...\...\....\.....\clk.bin
...\_xmsgs
...\__projnav
...\.........\clk.gfl
...\.........\clk.xst
...\.........\clk_flowplus.gfl
...\.........\createTF.err
...\.........\runXst_tcl.rsp
...\.........\sumrpt_tcl.rsp
...\__projnav.log

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