RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.

verilog实现简单risc
...................\Address_Register.v
...................\Address_Register.v.bak
...................\Alu_RISC.v
...................\Alu_RISC.v.bak
...................\Clock_Unit .v
...................\Control_Unit.v
...................\Control_Unit.v.bak
...................\D_flop.v
...................\Instruction_Register.v
...................\Instruction_Register.v.bak
...................\Memory_Unit.v
...................\Memory_Unit.v.bak
...................\Multiplexer_3ch.v
...................\Multiplexer_3ch.v.bak
...................\Multiplexer_5ch.v
...................\Multiplexer_5ch.v.bak
...................\Processing_Unit.v
...................\Processing_Unit.v.bak
...................\Program_Counter.v
...................\Program_Counter.v.bak
...................\Register_Unit.v
...................\Register_Unit.v.bak
...................\risc.cr.mti
...................\risc.mpf
...................\risc1.cr.mti
...................\risc1.mpf
...................\RSIC_SPM.v
...................\RSIC_SPM.v.bak
...................\test_RISC_SPM.v
...................\test_RISC_SPM.v.bak
...................\transcript
...................\vsim.wlf
...................\work
...................\....\@address_@register
...................\....\..................\verilog.asm
...................\....\..................\_primary.dat
...................\....\..................\_primary.dbs
...................\....\..................\_primary.vhd
...................\....\@alu_@r@i@s@c
...................\....\.............\verilog.asm
...................\....\.............\_primary.dat
...................\....\.............\_primary.dbs
...................\....\.............\_primary.vhd
...................\....\@clock_@unit
...................\....\............\verilog.asm
...................\....\............\_primary.dat
...................\....\............\_primary.dbs
...................\....\............\_primary.vhd
...................\....\@control_@unit
...................\....\..............\verilog.asm
...................\....\..............\_primary.dat
...................\....\..............\_primary.dbs
...................\....\..............\_primary.vhd
...................\....\@d_flop
...................\....\.......\verilog.asm
...................\....\.......\_primary.dat
...................\....\.......\_primary.dbs
...................\....\.......\_primary.vhd
...................\....\@instruction_@register
...................\....\......................\verilog.asm
...................\....\......................\_primary.dat
...................\....\......................\_primary.dbs
...................\....\......................\_primary.vhd
...................\....\@memory_@unit
...................\....\.............\verilog.asm
...................\....\.............\_primary.dat
...................\....\.............\_primary.dbs
...................\....\.............\_primary.vhd
...................\....\@multiplexer_3ch
...................\....\................\verilog.asm
...................\....\................\_primary.dat
...................\....\................\_primary.dbs
...................\....\................\_primary.vhd
...................\....\@multiplexer_5ch
...................\....\................\verilog.asm
...................\....\................\_primary.dat
...................\....\................\_primary.dbs
...................\....\................\_primary.vhd
...................\....\@processing_@unit
...................\....\.................\verilog.asm
...................\....\.................\_primary.dat
...................\....\.................\_primary.dbs
...................\....\.................\_primary.vhd
...................\....\@program_@counter
...................\....\.................\verilog.asm
...................\....\.................\_primary.dat
...................\....\.................\_primary.dbs
...................\....\.................\_primary.vhd
...................\....\@r@i@s@c_@s@p@m
...................\....\

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