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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 137kb
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  • Author :s*****
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Introduction - If you have any usage issues, please Google them yourself
Procedure provides a simple and efficient algorithm decoder 38, a very practical
Packet file list
(Preview for download)
38译码器
........\db
........\..\Vhdl2.asm.qmsg
........\..\Vhdl2.cbx.xml
........\..\Vhdl2.cmp.cdb
........\..\Vhdl2.cmp.hdb
........\..\Vhdl2.cmp.kpt
........\..\Vhdl2.cmp.logdb
........\..\Vhdl2.cmp.rdb
........\..\Vhdl2.cmp.tdb
........\..\Vhdl2.cmp0.ddb
........\..\Vhdl2.dbp
........\..\Vhdl2.db_info
........\..\Vhdl2.eco.cdb
........\..\Vhdl2.eds_overflow
........\..\Vhdl2.fit.qmsg
........\..\Vhdl2.hier_info
........\..\Vhdl2.hif
........\..\Vhdl2.map.cdb
........\..\Vhdl2.map.hdb
........\..\Vhdl2.map.logdb
........\..\Vhdl2.map.qmsg
........\..\Vhdl2.pre_map.cdb
........\..\Vhdl2.pre_map.hdb
........\..\Vhdl2.psp
........\..\Vhdl2.rtlv.hdb
........\..\Vhdl2.rtlv_sg.cdb
........\..\Vhdl2.rtlv_sg_swap.cdb
........\..\Vhdl2.sgdiff.cdb
........\..\Vhdl2.sgdiff.hdb
........\..\Vhdl2.signalprobe.cdb
........\..\Vhdl2.sim.hdb
........\..\Vhdl2.sim.qmsg
........\..\Vhdl2.sim.rdb
........\..\Vhdl2.sim.vwf
........\..\Vhdl2.sld_design_entry.sci
........\..\Vhdl2.sld_design_entry_dsc.sci
........\..\Vhdl2.syn_hier_info
........\..\Vhdl2.tan.qmsg
........\..\wed.zsf
........\Vhdl2.asm.rpt
........\Vhdl2.done
........\Vhdl2.fit.rpt
........\Vhdl2.fit.smsg
........\Vhdl2.fit.summary
........\Vhdl2.flow.rpt
........\Vhdl2.map.rpt
........\Vhdl2.map.summary
........\Vhdl2.pin
........\Vhdl2.qpf
........\Vhdl2.qsf
........\Vhdl2.qws
........\Vhdl2.sim.rpt
........\Vhdl2.tan.rpt
........\Vhdl2.tan.summary
........\Vhdl2.vhd
........\Vhdl2.vwf
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