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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 11kb
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  • Author :深***
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Introduction - If you have any usage issues, please Google them yourself
Four decimal frequency meter measuring frequency controller design includes (TESTCTL), 4 bit latch (REG4B), decimal counter (CNT10) of the original procedure (vhd), waveform file (wmf), packaged components (bsf). Top-level schematic document (Block1.bdf) and waveform.
Packet file list
(Preview for download)
交通灯
......\Block1.bdf
......\block1.vwf
......\cnt10.bsf
......\cnt10.vhd
......\cnt10.vwf
......\REG4B.bsf
......\REG4B.vhd
......\REG4B.vwf
......\TESTCTL.bsf
......\testctl.vhd
......\testctl.vwf
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