Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270

UART
....\cmp_state.ini
....\db
....\..\UART.asm.qmsg
....\..\UART.cbx.xml
....\..\UART.cmp.cdb
....\..\UART.cmp.hdb
....\..\UART.cmp.rdb
....\..\UART.cmp.tdb
....\..\UART.cmp0.ddb
....\..\UART.db_info
....\..\UART.eco.cdb
....\..\UART.fit.qmsg
....\..\UART.hier_info
....\..\UART.hif
....\..\UART.map.cdb
....\..\UART.map.hdb
....\..\UART.map.qmsg
....\..\UART.pre_map.cdb
....\..\UART.pre_map.hdb
....\..\UART.psp
....\..\UART.rtlv.hdb
....\..\UART.rtlv_sg.cdb
....\..\UART.rtlv_sg_swap.cdb
....\..\UART.sgdiff.cdb
....\..\UART.sgdiff.hdb
....\..\UART.signalprobe.cdb
....\..\UART.sld_design_entry.sci
....\..\UART.sld_design_entry_dsc.sci
....\..\UART.syn_hier_info
....\..\UART.tan.qmsg
....\UART.asm.rpt
....\UART.done
....\UART.fit.eqn
....\UART.fit.rpt
....\UART.fit.summary
....\UART.flow.rpt
....\UART.map.eqn
....\UART.map.rpt
....\UART.map.summary
....\UART.pin
....\UART.pof
....\UART.qpf
....\UART.qsf
....\UART.qws
....\UART.tan.rpt
....\UART.tan.summary
....\UART.vhd

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