16-order FIR filter - this design USES the VERILOG HDL language serial DA algorithm to realize the 16-order finite frequency response filter! -16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!

串行DA算法实现16阶FIR滤波器
...........................\da
...........................\..\adder_mac.v
...........................\..\ctrl_all.v
...........................\..\dacase8_1.v
...........................\..\dacase8_2.v
...........................\..\da_fir.prd
...........................\..\da_fir.prj
...........................\..\da_fir.qpf
...........................\..\DA_top.cr.mti
...........................\..\DA_top.mpf
...........................\..\DA_top.v
...........................\..\matlab_sim
...........................\..\..........\fir_da.m
...........................\..\..........\fir_da_tb.m
...........................\..\..........\gencase.m
...........................\..\MUX_16X1_M.v
...........................\..\Q_258_0_15_0_.mif
...........................\..\Q_258_0_15_0_mif1.mif
...........................\..\readme.txt
...........................\..\rev_3
...........................\..\.....\AutoConstraint_DA_top.sdc
...........................\..\.....\MUX_16X1_M.fse
...........................\..\.....\MUX_16X1_M.htm
...........................\..\.....\MUX_16X1_M.srd
...........................\..\.....\MUX_16X1_M.srm
...........................\..\.....\MUX_16X1_M.srr
...........................\..\.....\MUX_16X1_M.srs
...........................\..\.....\MUX_16X1_M.sxr
...........................\..\.....\MUX_16X1_M.tcl
...........................\..\.....\MUX_16X1_M.tlg
...........................\..\.....\MUX_16X1_M.vqm
...........................\..\.....\MUX_16X1_M.xrf
...........................\..\.....\MUX_16X1_M_cons.tcl
...........................\..\.....\MUX_16X1_M_rm.tcl
...........................\..\.....\par_1
...........................\..\.....\Q_258_0_15_0_.mif
...........................\..\.....\Q_258_0_15_0_mif1.mif
...........................\..\.....\rpt_DA_top.areasrr
...........................\..\.....\rpt_DA_top_areasrr.htm
...........................\..\.....\syntmp
...........................\..\.....\......\MUX_16X1_M.msg
...........................\..\.....\......\MUX_16X1_M.plg
...........................\..\.....\......\MUX_16X1_M_cons_ui.tcl
...........................\..\.....\......\MUX_16X1_M_flink.htm
...........................\..\.....\......\MUX_16X1_M_srr.htm
...........................\..\.....\......\MUX_16X1_M_toc.htm
...........................\..\.....\verif
...........................\..\.....\.....\MUX_16X1_M.vif
...........................\..\shift_ram.v
...........................\..\sim
...........................\..\...\adder_mac.v
...........................\..\...\ctrl_all.v
...........................\..\...\dacase8_1.v
...........................\..\...\dacase8_2.v
...........................\..\...\DA_top.v
...........................\..\...\DA_top_tb.v
...........................\..\...\imp_in.txt
...........................\..\...\MUX_16X1_M.v
...........................\..\...\shift_ram.v
...........................\..\veryclean.bat
...........................\..\work
...........................\..\....\@d@a_top
...........................\..\....\........\verilog.asm
...........................\..\....\........\_primary.dat
...........................\..\....\........\_primary.vhd
...........................\..\....\@d@a_top_tb
...........................\..\....\...........\verilog.asm
...........................\..\....\...........\_primary.dat
...........................\..\....\...........\_primary.vhd
...........................\..\....\@m@u@x_16@x1
...........................\..\....\............\verilog.asm
...........................\..\....\............\_primary.dat
...........................\..\....\............\_primary.vhd
...........................\..\....\adder_mac
...........................\..\....\.........\verilog.asm
...........................\..\....\.........\_primary.dat
...........................\..\....\.........\_primary.vhd
...........................\..\....\ctrl_all
...........................\..\....\........\verilog.asm
...........................\..\....\........\_primary.dat
......

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