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cpuyuanma1

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 726kb
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  • Author :che****
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Description: cpuyuanma1 hard wiring the controller source code, cpuyuanma2 micro-program controller source code.
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1.11 组合逻辑控制器部件实验
...........................\cmp_state.ini
...........................\cpu.asm.rpt
...........................\cpu.done
...........................\cpu.fit.eqn
...........................\cpu.fit.rpt
...........................\cpu.fit.summary
...........................\cpu.flow.rpt
...........................\cpu.map.eqn
...........................\cpu.map.rpt
...........................\cpu.map.summary
...........................\cpu.pin
...........................\cpu.pof
...........................\cpu.qpf
...........................\cpu.qsf
...........................\cpu.qws
...........................\cpu.tan.rpt
...........................\cpu.tan.summary
...........................\cpu.vhd
...........................\cpu_assignment_defaults.qdf
...........................\cpu_comm.sof
...........................\cpu_defs.vhd
...........................\db
...........................\..\add_sub_4ih.tdf
...........................\..\add_sub_5ih.tdf
...........................\..\cpu.asm.qmsg
...........................\..\cpu.cbx.xml
...........................\..\cpu.cmp.cdb
...........................\..\cpu.cmp.hdb
...........................\..\cpu.cmp.rdb
...........................\..\cpu.cmp.tdb
...........................\..\cpu.cmp0.ddb
...........................\..\cpu.db_info
...........................\..\cpu.eco.cdb
...........................\..\cpu.fit.qmsg
...........................\..\cpu.hier_info
...........................\..\cpu.hif
...........................\..\cpu.map.cdb
...........................\..\cpu.map.hdb
...........................\..\cpu.map.qmsg
...........................\..\cpu.pre_map.cdb
...........................\..\cpu.pre_map.hdb
...........................\..\cpu.psp
...........................\..\cpu.rtlv.hdb
...........................\..\cpu.rtlv_sg.cdb
...........................\..\cpu.rtlv_sg_swap.cdb
...........................\..\cpu.sgdiff.cdb
...........................\..\cpu.sgdiff.hdb
...........................\..\cpu.sld_design_entry.sci
...........................\..\cpu.sld_design_entry_dsc.sci
...........................\..\cpu.smp_dump.txt
...........................\..\cpu.syn_hier_info
...........................\..\cpu.tan.qmsg
...........................\..\cpu_cmp.qrpt
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