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cpuyuanma2

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 125kb
  • Downloaded :0次
  • Author :che****
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Introduction - If you have any usage issues, please Google them yourself
This is then the above procedures, micro-program controller source code, debugging has been adopted.
Packet file list
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1.12 微程序控制器部件实验
.........................\cmp_state.ini
.........................\CPU.asm.rpt
.........................\CPU.done
.........................\CPU.fit.eqn
.........................\CPU.fit.rpt
.........................\CPU.fit.summary
.........................\CPU.flow.rpt
.........................\CPU.map.eqn
.........................\CPU.map.rpt
.........................\CPU.map.summary
.........................\CPU.pin
.........................\CPU.pof
.........................\CPU.qpf
.........................\CPU.qsf
.........................\CPU.qws
.........................\CPU.tan.rpt
.........................\CPU.tan.summary
.........................\cpu.vhd
.........................\CPU_assignment_defaults.qdf
.........................\cpu_defs.vhd
.........................\cpu_micro.sof
.........................\db
.........................\..\add_sub_4ih.tdf
.........................\..\add_sub_5ih.tdf
.........................\..\CPU.db_info
.........................\..\CPU.eco.cdb
.........................\..\CPU.sld_design_entry.sci
.........................\..\CPU_cmp.qrpt
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