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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 3.67mb
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Packet file list
(Preview for download)
lab2
....\bitinit.log
....\blkdiagram
....\..........\lab2.css
....\..........\lab2.html
....\..........\lab2.svg
....\..........\svg10.dtd
....\data
....\....\lab2.ucf
....\etc
....\...\bitgen.ut
....\...\download.cmd
....\...\fast_runtime.opt
....\hdl
....\...\dcm_0_wrapper.vhd
....\...\debug_module_wrapper.vhd
....\...\dip_wrapper.vhd
....\...\dlmb_cntlr_wrapper.vhd
....\...\dlmb_wrapper.vhd
....\...\elaborate
....\...\.........\lmb_bram_elaborate_v1_00_a
....\...\.........\..........................\hdl
....\...\.........\..........................\...\vhdl
....\...\.........\..........................\...\....\lmb_bram_elaborate.vhd
....\...\ilmb_cntlr_wrapper.vhd
....\...\ilmb_wrapper.vhd
....\...\lab2.vhd
....\...\lab2_stub.vhd
....\...\leds_8bit_wrapper.vhd
....\...\lmb_bram_wrapper.vhd
....\...\mb_opb_wrapper.vhd
....\...\microblaze_0_wrapper.vhd
....\...\push_wrapper.vhd
....\...\rs232_dce_wrapper.vhd
....\implementation
....\..............\bitgen.ut
....\..............\cache
....\..............\.....\cache.cat
....\..............\.....\dcm_0_wrapper.ngc
....\..............\.....\debug_module_wrapper.ngc
....\..............\.....\dip_wrapper.ngc
....\..............\.....\dlmb_cntlr_wrapper.ngc
....\..............\.....\dlmb_wrapper.ngc
....\..............\.....\ilmb_cntlr_wrapper.ngc
....\..............\.....\ilmb_wrapper.ngc
....\..............\.....\leds_8bit_wrapper.ngc
....\..............\.....\lmb_bram_wrapper.ngc
....\..............\.....\mb_opb_wrapper.ngc
....\..............\.....\microblaze_0_wrapper.ngc
....\..............\.....\push_wrapper.ngc
....\..............\.....\rs232_dce_wrapper.ngc
....\..............\dcm_0_wrapper
....\..............\dcm_0_wrapper.ngc
....\..............\dcm_0_wrapper_vhdl.prj
....\..............\debug_module_wrapper
....\..............\debug_module_wrapper.ngc
....\..............\debug_module_wrapper_vhdl.prj
....\..............\dip_wrapper
....\..............\dip_wrapper.ngc
....\..............\dip_wrapper_vhdl.prj
....\..............\dlmb_cntlr_wrapper
....\..............\dlmb_cntlr_wrapper.ngc
....\..............\dlmb_cntlr_wrapper_vhdl.prj
....\..............\dlmb_wrapper
....\..............\dlmb_wrapper.ngc
....\..............\dlmb_wrapper_vhdl.prj
....\..............\download.bit
....\..............\fpga.flw
....\..............\ilmb_cntlr_wrapper
....\..............\ilmb_cntlr_wrapper.ngc
....\..............\ilmb_cntlr_wrapper_vhdl.prj
....\..............\ilmb_wrapper
....\..............\ilmb_wrapper.ngc
....\..............\ilmb_wrapper_vhdl.prj
....\..............\lab2.bgn
....\..............\lab2.bit
....\..............\lab2.bld
....\..............\lab2.bmm
....\..............\lab2.drc
....\..............\lab2.ncd
....\..............\lab2.ngc
....\..............\lab2.ngd
....\..............\lab2.pad
....\..............\lab2.par
....\..............\lab2.pcf
....\..............\lab2.twr
....\..............\lab2.twx
....\..............\lab2.ucf
....\..............\lab2.unroutes
....\..............\lab2.xpi
....\..............\lab2_bd.bmm
....\..............\lab2_map.map
....\..............\lab2_map.mrp
....\..............\lab2_map.ncd
....\..............\lab2_map.ngm
....\..............\lab2_pad.csv
....\..............\lab2_pad.txt
....\..............\lab2_stub.bmm
....\..............\lab2_summary.xml
....\..............\lab2_usage.xml
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