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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 984kb
  • Downloaded :0次
  • Author :zhu****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
XLINX do digital clock can be accurately timed. With counters and flip-flops to achieve.
Packet file list
(Preview for download)
数字钟
......\alarm.cmd_log
......\alarm.lso
......\alarm.ngc
......\alarm.ngr
......\alarm.prj
......\alarm.sch
......\alarm.stx
......\alarm.sym
......\alarm.synth_nlf
......\alarm.syr
......\alarm.vhdsim_synth
......\alarm.vhf
......\alarm_summary.html
......\alarm_synthesis.nlf
......\alarm_synthesis.vhd
......\automake.log
......\bitgen.ut
......\clock.bgn
......\clock.bit
......\CLOCK.bld
......\CLOCK.cmd_log
......\clock.drc
......\CLOCK.lfp
......\CLOCK.lso
......\CLOCK.mrp
......\CLOCK.nc1
......\CLOCK.ncd
......\CLOCK.ngc
......\CLOCK.ngd
......\CLOCK.ngm
......\CLOCK.ngr
......\CLOCK.pad
......\CLOCK.pad_txt
......\CLOCK.par
......\CLOCK.pcf
......\CLOCK.placed_ncd_tracker
......\CLOCK.prj
......\CLOCK.routed_ncd_tracker
......\CLOCK.sch
......\CLOCK.schbak
......\CLOCK.schcmd
......\CLOCK.stx
......\CLOCK.synth_nlf
......\CLOCK.syr
......\clock.twr
......\clock.twx
......\CLOCK.ucf
......\CLOCK.ucf.untf
......\CLOCK.ut
......\CLOCK.vhd
......\CLOCK.vhdsim_synth
......\CLOCK.vhf
......\CLOCK.xpi
......\CLOCK_last_par.ncd
......\CLOCK_map.ncd
......\CLOCK_map.ngm
......\CLOCK_pad.csv
......\CLOCK_pad.txt
......\CLOCK_summary.html
......\CLOCK_synthesis.nlf
......\CLOCK_synthesis.vhd
......\Hour.cmd_log
......\Hour.sch
......\Hour.schlog
......\Hour.sym
......\Hour.vhf
......\pepExtractor.prj
......\Plus60.cmd_log
......\Plus60.ldo
......\Plus60.sch
......\Plus60.schbak
......\Plus60.schcmd
......\Plus60.sym
......\Plus60.vhf
......\Plus60_summary.html
......\results.txt
......\TEST241.ant
......\TEST241.fdo
......\TEST241.jhd
......\TEST241.tbw
......\TEST241.udo
......\TEST241.vhw
......\TEST241.xwv
......\TEST241.xwv_bak
......\TEST241_bencher.prj
......\TEST242.ant
......\TEST242.fdo
......\TEST242.jhd
......\TEST242.tbw
......\TEST242.udo
......\TEST242.vhw
......\TEST242.xwv
......\TEST242.xwv_bak
......\TEST242_bencher.prj
......\test60.ant
......\TEST60.fdo
......\test60.tbw
......\TEST60.udo
......\test60.vhw
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