Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing, adder module ahead of the last bit adder, including test bed, through the Modelsim, Synplify simulation.

4bit_buma_adder
...............\adder.v
...............\adderfms.v
...............\add_top.v

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