[Other resource] yiraomis

Description: a complete medical-management system. Do not for commercial use!
Platform: | Size: 5237712 | Author: 戴利坚 | Hits:

[Other resource] enhancement

Description: the image processing of Matlab source, including contrast enhancement, histogram homogenization, and filtering. If interested welcome to download.
Platform: | Size: 33076 | Author: 李连春 | Hits:

[Other resource] rtcticket实验（实时时钟）

Description: ARM7 rtcticket Experiment (real-time clock), the clock may help learning
Platform: | Size: 99410 | Author: 百里情愁 | Hits:

[Other resource] 地图图元修改工具

Description: map plan amendments yuan batch tools can be selected to amend the map layer map yuan Style.
Platform: | Size: 16480 | Author: 王静 | Hits:

[Other resource] 8255按键练习

Description: 8,255 inquiries through the keys, show different figures. K1 shows a, K2 showed 2, K1 and K2 showed three, and so forth. The most that can be shown 7.
Platform: | Size: 14056 | Author: SKY | Hits:

[Other resource] 32位-33M 从模式(target)PCI接口参考设计_lattice

Description: 32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
Platform: | Size: 826676 | Author: 陈旭 | Hits:

[Other resource] 8051参考设计_Oregano System 提供_vhdl

Description: 8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
Platform: | Size: 664567 | Author: 陈旭 | Hits:

[Other resource] CRC校验参考设计_xilinx_verilog

Description: IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
Platform: | Size: 89932 | Author: 陈旭 | Hits:

[Other resource] CRC校验参考设计_xilinx_vhdl

Description: configurable CRC reference design for Xilinx VHDL
Platform: | Size: 49875 | Author: 陈旭 | Hits:

[Other resource] DS12887时钟芯片编程

Description: procedures for the use of function, to read clock chip seconds, hours, days, months, years, centuries, but also the date of its set-up time.
Platform: | Size: 18776 | Author: SKY | Hits:

[Other resource] 红绿灯

Description: simulated traffic lights and figures with the procedure. When all of the initial red, shows that the "hello" words. Then traffic lights to the "black, red and yellow, green, red, yellow red" state to do four cycle, but t
Platform: | Size: 25843 | Author: SKY | Hits:

[Other resource] ddr_verilog_xilinx

Description: DDR (double data rate) SDRAM controller reference design for Xilinx
Platform: | Size: 131327 | Author: 陈旭 | Hits: