[Other resource] 32位-33M 从模式(target)PCI接口参考设计_lattice

Description: 32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
Platform: | Size: 826676 | Author: 陈旭 | Hits:

[Other resource] 8051参考设计_Oregano System 提供_vhdl

Description: 8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
Platform: | Size: 664567 | Author: 陈旭 | Hits:

[Other resource] CRC校验参考设计_xilinx_verilog

Description: IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
Platform: | Size: 89932 | Author: 陈旭 | Hits:

[Other resource] CRC校验参考设计_xilinx_vhdl

Description: configurable CRC reference design for Xilinx VHDL
Platform: | Size: 49875 | Author: 陈旭 | Hits:

[Other resource] DS12887时钟芯片编程

Description: procedures for the use of function, to read clock chip seconds, hours, days, months, years, centuries, but also the date of its set-up time.
Platform: | Size: 18776 | Author: SKY | Hits:

[Other resource] 红绿灯

Description: simulated traffic lights and figures with the procedure. When all of the initial red, shows that the "hello" words. Then traffic lights to the "black, red and yellow, green, red, yellow red" state to do four cycle, but t
Platform: | Size: 25843 | Author: SKY | Hits:

[Other resource] ddr_verilog_xilinx

Description: DDR (double data rate) SDRAM controller reference design for Xilinx
Platform: | Size: 131327 | Author: 陈旭 | Hits:

[Other resource] 洗衣机

Description: through different diode light, washing machines, said the different states. Who is changed, and turned around, washing, drying. Press P3_3, would cease.
Platform: | Size: 24225 | Author: SKY | Hits:

[Other resource] 显示0到F

Description: drive using serial digital display shows each from 0 to F, to eliminate cycle, a request updated seconds.
Platform: | Size: 10852 | Author: SKY | Hits:

[Other resource] dds_quicklogic

Description: direct frequency synthesis, pioneered provide some source document is dedicated ESP
Platform: | Size: 68450 | Author: 陈旭 | Hits:

[Other resource] I2C总线控制器 altera提供-VHDL

Description: I2C Bus Controller ALTERA the VHDL source code
Platform: | Size: 1639890 | Author: 陈旭 | Hits:

[Other resource] PCI总线仲裁参考设计，Quicklogic提供

Description: PCI bus arbitration reference design, pioneered the Verilog code
Platform: | Size: 3480 | Author: 陈旭 | Hits: