Other resource List Page 11105

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《Franklin C-51程序设计》 Downloaded：0: "Franklin C-51 Programming" the classics cross the threshold
Date : 2008-10-13 Size : 53.26kb User : 刘超
3线双向零等待IO通讯机制 Downloaded：0: 3 bidirectional zero waited for the IO communication machine-made monolithic integrated circuit communication source code belt explained
Date : 2008-10-13 Size : 2kb User : 刘超
单片机C语言音乐程序的制作方法 Downloaded：0: Monolithic integrated circuit C language music procedure source program (KeilC code)
Date : 2008-10-13 Size : 18.86kb User : 刘超
我自己写的RFID读写程序(U2270) Downloaded：1: I write the RFID read-write procedure (U2270) refers for everybody
Date : 2008-10-13 Size : 154.37kb User : 刘超
GA-1_cpp Downloaded：0: Indefinite plan heredity algorithm Nonlinear Programming algorithm procedure
Date : 2008-10-13 Size : 1.8kb User : 家
ucosII_arm_source Downloaded：1: UCOS- II ARM code (4510B)
Date : 2008-10-13 Size : 172.16kb User : 刘超
GA-2_cpp Downloaded：0: Indefinite plan heredity algorithm Goal Programming algorithm procedure
Date : 2008-10-13 Size : 1.83kb User : 家
GA-3_cpp Downloaded：0: Indefinite plan heredity algorithm Multilevel Programming algorithm procedure
Date : 2008-10-13 Size : 2.95kb User : 家
ClkScan Downloaded：0: This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC)
Date : 2008-10-13 Size : 896.04kb User : huhu
qdq_new Downloaded：0: Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divide is three parts: The sampling electric
Date : 2008-10-13 Size : 64.03kb User : huhu
second&clk Downloaded：0: Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes
Date : 2008-10-13 Size : 328.8kb User : huhu
Music_altera Downloaded：0: Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music
Date : 2008-10-13 Size : 637.12kb User : huhu

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