VHDL language to achieve the UART IP core, more practical

uartvhdl
........\address_decode_rtl.vhd
........\clock_divider.v
........\control_operation_fsm.vhd
........\cpu_interface_rtl.vhd
........\serial_interface_rtl.vhd
........\status_registers_rtl.vhd
........\tester.v
........\UART 源码 (lattice version).rar
........\uart 源码 (Verilog).zip
........\uart 源码 (VHDL).zip
........\uart16550.tar.gz
........\uart_tb.v
........\uart_top_rtl.vhd
........\uart_vhdl_lattice
........\.................\intface.vhd
........\.................\modem.vhd
........\.................\rxcver.vhd
........\.................\txmitt.vhd
........\.................\uart_5kvg_top.vhd
........\.................\uart_an_lattice.pdf
........\.................\uart_int_tb.vhd
........\.................\uart_rxerr_tb.vhd
........\.................\uart_rx_tb.vhd
........\.................\uart_top.vhd
........\.................\uart_tx_tb.vhd
........\xmit_rcv_control_fsm.vhd

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