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VerilogHDLDigitalControlSystemExample

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 10.85mb
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  • Author :王****
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Verilog HDL Digital Control System Design - Xian Jin- source code
Packet file list
(Preview for download)
第1章
.....\counter_4_bit
.....\.............\cmp_state.ini
.....\.............\counter_4_bit.asm.rpt
.....\.............\counter_4_bit.done
.....\.............\counter_4_bit.fit.eqn
.....\.............\counter_4_bit.fit.rpt
.....\.............\counter_4_bit.fit.summary
.....\.............\counter_4_bit.flow.rpt
.....\.............\counter_4_bit.map.eqn
.....\.............\counter_4_bit.map.rpt
.....\.............\counter_4_bit.map.summary
.....\.............\counter_4_bit.pin
.....\.............\counter_4_bit.pof
.....\.............\counter_4_bit.qpf
.....\.............\counter_4_bit.qsf
.....\.............\counter_4_bit.qws
.....\.............\counter_4_bit.sim.rpt
.....\.............\counter_4_bit.tan.rpt
.....\.............\counter_4_bit.tan.summary
.....\.............\counter_4_bit.v
.....\.............\counter_4_bit.vwf
.....\.............\db
.....\.............\..\counter_4_bit.asm.qmsg
.....\.............\..\counter_4_bit.cmp.cdb
.....\.............\..\counter_4_bit.cmp.ddb
.....\.............\..\counter_4_bit.cmp.hdb
.....\.............\..\counter_4_bit.cmp.rdb
.....\.............\..\counter_4_bit.cmp.tdb
.....\.............\..\counter_4_bit.cmp0.ddb
.....\.............\..\counter_4_bit.db_info
.....\.............\..\counter_4_bit.eco.cdb
.....\.............\..\counter_4_bit.eds_overflow
.....\.............\..\counter_4_bit.fit.qmsg
.....\.............\..\counter_4_bit.hier_info
.....\.............\..\counter_4_bit.hif
.....\.............\..\counter_4_bit.map.cdb
.....\.............\..\counter_4_bit.map.hdb
.....\.............\..\counter_4_bit.map.qmsg
.....\.............\..\counter_4_bit.pre_map.cdb
.....\.............\..\counter_4_bit.pre_map.hdb
.....\.............\..\counter_4_bit.psp
.....\.............\..\counter_4_bit.rtlv.hdb
.....\.............\..\counter_4_bit.rtlv_sg.cdb
.....\.............\..\counter_4_bit.rtlv_sg_swap.cdb
.....\.............\..\counter_4_bit.sgdiff.cdb
.....\.............\..\counter_4_bit.sgdiff.hdb
.....\.............\..\counter_4_bit.sim.hdb
.....\.............\..\counter_4_bit.sim.qmsg
.....\.............\..\counter_4_bit.sim.rdb
.....\.............\..\counter_4_bit.sim.vwf
.....\.............\..\counter_4_bit.sld_design_entry.sci
.....\.............\..\counter_4_bit.sld_design_entry_dsc.sci
.....\.............\..\counter_4_bit.syn_hier_info
.....\.............\..\counter_4_bit.tan.qmsg
.....\.............\..\counter_4_bit_cmp.qrpt
.....\.............\..\counter_4_bit_sim.qrpt
.....\num1_1
.....\......\cmp_state.ini
.....\......\db
.....\......\..\num1_1.asm.qmsg
.....\......\..\num1_1.cmp.cdb
.....\......\..\num1_1.cmp.ddb
.....\......\..\num1_1.cmp.hdb
.....\......\..\num1_1.cmp.rdb
.....\......\..\num1_1.cmp.tdb
.....\......\..\num1_1.cmp0.ddb
.....\......\..\num1_1.db_info
.....\......\..\num1_1.eco.cdb
.....\......\..\num1_1.eds_overflow
.....\......\..\num1_1.fit.qmsg
.....\......\..\num1_1.hier_info
.....\......\..\num1_1.hif
.....\......\..\num1_1.map.cdb
.....\......\..\num1_1.map.hdb
.....\......\..\num1_1.map.qmsg
.....\......\..\num1_1.pre_map.cdb
.....\......\..\num1_1.pre_map.hdb
.....\......\..\num1_1.psp
.....\......\..\num1_1.rtlv.hdb
.....\......\..\num1_1.rtlv_sg.cdb
.....\......\..\num1_1.rtlv_sg_swap.cdb
.....\......\..\num1_1.sgdiff.cdb
.....\......\..\num1_1.sgdiff.hdb
.....\......\..\num1_1.sim.hdb
.....\......\..\num1_1.sim.qmsg
.....\......\..\num1_1.sim.rdb
.....\......\..\num1_1.sim.vwf
.....\......\..\num1_1.sld_design_entry.sci
.....\......\..\num1_1.sld_design_entry_dsc.sci
.....\......\..\num1_1.syn_hier_info
.....\......\..\num1_1.tan.qmsg
.....\......\..\num1_1_cmp.qrpt
.....\......\..\num1_1_sim.qrpt
.....\......\num1_1.asm.rpt
.....\......\num1_1.done
.....\......\num1_1.fit.eqn
.....\......\num1_1.fit.rpt
.....\......\num1_1.fit.summary
.....\......\num1_1.flow.rpt
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