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Title:
fir_finall
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
1.2kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
liudong1022
Description:
verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
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