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Title:
COUNT_10
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Category:
VHDL-FPGA-Verilog
Tags:
File Size:
928byte
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
fuxiaoyi2008
Description:
VHDL source code. Asynchronous design with a 0-counter function of the metric system. Counter clock clk ascending effective end to reset clrn, rounding output co.
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