Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads Develop Tools
Title: 32bits_float_muliplier Download
  • Category:
  • E-Books
  • Tags:
  • [WORD]
  • File Size:
  • 94.78kb
  • Update:
  • 2008-10-13
  • Downloads:
  • 2 Times
  • Uploaded by:
  • mcux
 Description: 32-bit floating-point multiplier design, speak very good, and for reference ah
 Downloaders recently: [More information of uploader mcux]
 To Search: 32bits_float_muliplier floating point multiplier
  • [fft_debug] - can float for 32 fft Operational VHDL de
  • [FPGA_common] - on FPGA with some common sense and VHDL
  • [verilog_multiplier] - verilog achieve 16* 16 multiplier, with
  • [cpupipeline] - CPU design, adders, multiplier, divider
  • [Gps25Comm] - GPS receiver data monitoring program---
  • [EDA] - There is a FIR filter design report ther
  • [floatmul] - Verilog design language used to achieve
  • [multiply] - This is my verilog hdl language used to
  • [32bit_multiplexer] - 32-bit high-performance floating-point m
  • [mul64] - A 64-bit multiplier design an experiment
File list (Check if you may need any files):

CodeBus www.codebus.net