Description: The module is the working principle is to parallel input from state control module with two sets of parallel output signals corresponding to high and low level for comparison. If the corresponding state of the same output as one, otherwise to 0. Map A0-A9 parallel code for the A group clk0 for the clock signal, z In order to compare the output.
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- [s_pandp_s] - prepared using VHDL and string conversio
- [Mov9] - Realize this project is 9 Sememe transfo
- [c100] - There are on the C language source code
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