Description: VHDL design of 26 cases of classic - in xilinx chip debugging through, [01 - one full adder] [02-2 choose 1 multi-channel selector] [03 - eight hardware adder] [04-7 digital display decoder] [05-8 bit string into and out of the register] [6-8 into A string of the register] [7 - internal tristate bus] [8 -- including reset and synchronous clock can make four addition counter] [9] - CNC divider [10 -- four decimal frequency meter] [11 - decoding scanning display circuit] [12 -- A state machine is used to implement the design of sequential detector] [13 - with the state machine of ADC0832 circuit control realization of sine function generator] [14 - the state machine is used to implement ADC0809 sampling circuit design] [15 - DMA way A/D sampling control circuit design] [16 - hardware keyboard] [17 - automatically play music] [18 -- A stopwatch] [19 -- add eight hardware multiplier) [20 -- VGA display controller (striped)] [21] -- VGA display controller [22 -- such as precision frequency meter] [23 - simulation waveform generator] [24 - analog oscilloscope] [25 -- general asynchronous transceiver (UART)] [26 -- 8-bit CPU design (COP2000)]
- [ISE_uart] - in ISE using VHDL was the UART, simple,
- [electronic_organ_desin] - FPGA-based design of a flower, the flowe
- [myUART] - This is the company I used the sparten3
- [vhdl_clock] - VHDL digital clock, the use of digital c
- [sn] - Xilinx ISE9.2 annex for the installation
- [divider] - Introduced the divider design, using ver
- [verilog_delta_complete] - Verilog designs sawtooth waveform module
- [digital_cymometer] - Simple digital frequency meter using com
- [SRAM] - FPGA control SRAM61LV25616 vhdl source.
- [JPEGvhdl] - JPEG image compression standard works of
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