Description: GAL16V8D based on a clock the whole logic of the code to open. Verilog prepared!
- [pld] - from feng prepared by the entry PLD good
- [ispLEVERTrainingGuide.Zip] - ispLEVER CPLD, FPGA development environm
- [16V8] - This is AHDL is abel language programmab
- [galpld] - gal programming tool, although it is now
- [GAL] - Examples of a combinational logic to com
- [gal] - Series can be used to edit the chips use
- [NeighborInfo] - Can not scan the missing LAN host surviv
- [jiangxi_voIP] - Jiangxi public IP telephone network feas
- [adgal] - This code can be used as a programmable
- [GAL16V8] - GAL16v8 programming, cupl language, GAL
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