Description: There is a 5 on the interleaver of the source code, are interested in learning what can be down
- [interleave] - -Verilog code for interleave.
- [wcdma_simulink] - two researchers write the W-CDMA simulat
- [PCMsdgl] - PCM channel selection filters C language
- [Turbo_simulink_no_punc] - Turbo classical simulation links, links
- [STC89C516RD+_es51] - ES51 plate KELL C51 source can be the so
- [Interleave] - In Maxplus software platform developed u
- [jiaozhi] - Suitable for wireless communication chan
- [ofdm_modu] - OFDM FPGA using the Verilog procedures r
- [4_31] - This is an interleaver/de-interleaver to
- [interleaver] - Veriog interwoven matrix of the realizat
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