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Title:
uart_0
Download
Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
5.31kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
baixue3044
Description:
Asynchronous serial communication UART Interface Design, Verilog HDL procedures essential embedded Oh
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