digital_clock verlog language with a good addendum - CodeBus

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Title: digital_clock

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
266.89kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
leolili1212

Description: verlog language with a good addendum to the comprehensive experiment, particularly suitable for FPGA/CPLD beginners

Downloaders recently: [More information of uploader leolili1212]

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