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Title:
rtl
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
4.03kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
wzq123s
Description:
JTAG design verilog code.
Downloaders recently:
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More information of uploader wzq123s
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