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Title:
ethernet__verilog
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Category:
VHDL-FPGA-Verilog
Tags:
[PDF]
File Size:
323.51kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
w200114
Description:
FPGA simulation of the Ethernet physical layer of the source code, using Verilog hardware description language development.
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More information of uploader w200114
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fpga
Verilog ethernet
ethernet
ethernet verilog
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