Description: Quartus under the RS (5,3) encoder source code, using Verilog language.
- [RSencoder(Verilog)] - RS coding using the source code in Veril
- [rs-codec-8-16] - This is a rs decoder running on Verilog
- [USB_VHDL] - USB bus interface of the VHDL realize, I
- [viterbi] - VHDL procedures vertibe realize the enco
- [16b20b] - Ethernet 16B/20B source code including t
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