Description: Development environment is the FPGA development tools, Gray code counter VHDL procedures
- [severalencoding.Rar] - have a length of 1,000 random binary seq
- [GrayCounter] - Counter, can counter by the binary count
- [CSerialPort] - cserialport.h good use serial communicat
- [PS_usp_rspfile] - This procedure can be a given piece of p
- [GrayCode] - Gray code counters, as well as treatment
- [mapping_sequence] - mapping the deta serial into GeLei code,
- [p5] - Tutorial CODE conversors binary-gray and
- [gray_cnt] - A Gray-code counters, the use of Verilog
- [graycnt_3] - 3 Gray code counter verilog description
- [graycnt_14] - 14-bit Gray code counter verilog descrip
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