d02 This procedure for pulse width measurement cir

Title: d02

Category:
VHDL-FPGA-Verilog
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File Size:
2.31kb
Update:
2008-10-13
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464151479

Description: This procedure for pulse width measurement circuit VHDL code, able to input the pulse signal with 10Hz clock count, the output result of the calculation. Main module calls show that counts, control the main functions of the three modules realize

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