Dual_port_RAM
.............\component
.............\constraint
.............\coreconsole
.............\designer
.............\........\impl1
.............\........\.....\designer_genhdl.log
.............\........\.....\Doul_RAM.tcl
.............\........\.....\simulation
.............\Dual_port_RAM.prj
.............\hdl
.............\...\ctrl_doul_RAM.v
.............\...\hdlsynchk.tcl
.............\...\top.v
.............\phy_synthesis
.............\simulation
.............\..........\Doul_RAM_R0C0.mem
.............\..........\meminit.dat
.............\..........\modelsim.ini
.............\..........\modelsim.ini.sav
.............\..........\modelsim.log
.............\..........\presynth
.............\..........\........\@doul_@r@a@m
.............\..........\........\............\verilog.psm
.............\..........\........\............\_primary.dat
.............\..........\........\............\_primary.vhd
.............\..........\........\read_wirte_ram
.............\..........\........\..............\verilog.psm
.............\..........\........\..............\_primary.dat
.............\..........\........\..............\_primary.vhd
.............\..........\........\stimulus
.............\..........\........\........\verilog.psm
.............\..........\........\........\_primary.dat
.............\..........\........\........\_primary.vhd
.............\..........\........\tb_clock_minmax
.............\..........\........\...............\verilog.psm
.............\..........\........\...............\_primary.dat
.............\..........\........\...............\_primary.vhd
.............\..........\........\testbench
.............\..........\........\.........\verilog.psm
.............\..........\........\.........\_primary.dat
.............\..........\........\.........\_primary.vhd
.............\..........\........\top
.............\..........\........\...\verilog.psm
.............\..........\........\...\_primary.dat
.............\..........\........\...\_primary.vhd
.............\..........\........\_info
.............\..........\........\_temp
.............\..........\run.do
.............\..........\vsim.wlf
.............\..........\wave.do
.............\smartgen
.............\........\Doul_RAM
.............\........\........\Doul_RAM.cxf
.............\........\........\Doul_RAM.gen
.............\........\........\Doul_RAM.log
.............\........\........\Doul_RAM.shx
.............\........\........\Doul_RAM.v
.............\........\........\Doul_RAM_R0C0.mem
.............\........\Doul_RAM_work.ixf
.............\........\smartgen.aws
.............\stimulus
.............\........\BtimErrors.log
.............\........\Doul_RAM.dsk
.............\........\Doul_RAM.hpj
.............\........\files_to_build.txt
.............\........\top.dsk
.............\........\top.hpj
.............\........\top_tbench.bk
.............\........\top_tbench.btim
.............\........\top_tbench.v
.............\........\waveperl.log
.............\synthesis
.............\.........\Doul_RAM.areasrr
.............\.........\Doul_RAM.edn
.............\.........\Doul_RAM.fse
.............\.........\Doul_RAM.htm
.............\.........\Doul_RAM.map
.............\.........\Doul_RAM.sap
.............\.........\Doul_RAM.sdf
.............\.........\Doul_RAM.srd
.............\.........\Doul_RAM.srm
.............\.........\Doul_RAM.srr
.............\.........\Doul_RAM.srs
.............\.........\Doul_RAM.tlg
.............\.........\Doul_RAM.v
.............\.........\Doul_RAM_drc.rpt
.............\.........\Doul_RAM_sdc.sdc
.............\.........\Doul_RAM_syn.prj
.............\.........\stdout.log
.............\.........\syntmp
.............\.........\......\Doul_RAM.msg
.............\.........\......\Doul_RAM.plg
.............\.........\......\Doul_RAM_flink.htm
.............\.........\......\Doul_RAM_srr.htm
.............\.........\......\Doul_RAM_toc.htm
.............\.........\......\sap.log
.............\viewdraw
.............\........\sch
.............\........\sym