Description: cpu design example mips. MIPSI instruction set 32-bit CPU
(1) MiniCore design example of the entire 32-bit operation, 32 32-bit general-purpose registers, all the commands and addresses are all 32-bit (2) static line (3 ~ 5)
(3) Forwarding technology (4 )-chip L1 Cache, command, data of all 4KByte, hardware initialization
(5) there is no TLB, but the system control coprocessor (CP0) with the exception of pages outside the full functionality of mapping
- [pipe] - Verilog modules prepared by the Pipeline
- [sarm9beta] - arm9 core framework to achieve a simple,
- [cache] - original verilog HDL achieve CACHE opera
- [leg_source] - verilog hdl prepared replace pipelined C
- [CPU] - Use verilog as CPU design language to im
- [TestCache] - The use of C++ Language programming meas
- [MIPS] - Branch prediction with the MIPS pipeline
- [branch_prediction_simulatot] - five branch prediction simulators of com
- [liu] - Liu Rujia _ exercise guide book, with Li
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cpu设计实例mips.ppt
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