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Title: work2 Download
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  • 197kb
  • Update:
  • 2012-11-26
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  • 472704739
 Description: Designed by 74181 and 74182 of an 8-bit arithmetic logic unit has been through simulation ~~~~~~~~~~~~~~~~~~~~~
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File list (Check if you may need any files):
work2
.....\and-2.asm.rpt
.....\and-2.bdf
.....\and-2.done
.....\and-2.fit.eqn
.....\and-2.fit.rpt
.....\and-2.fit.summary
.....\and-2.flow.rpt
.....\and-2.map.eqn
.....\and-2.map.rpt
.....\and-2.map.summary
.....\and-2.pin
.....\and-2.qpf
.....\and-2.qsf
.....\and-2.qws
.....\and-2.sim.rpt
.....\and-2.tan.rpt
.....\and-2.tan.summary
.....\and-2.vwf
.....\db
.....\..\and-2.asm.qmsg
.....\..\and-2.cbx.xml
.....\..\and-2.cmp.cdb
.....\..\and-2.cmp.hdb
.....\..\and-2.cmp.qrpt
.....\..\and-2.cmp.rdb
.....\..\and-2.cmp.tdb
.....\..\and-2.cmp0.ddb
.....\..\and-2.dbp
.....\..\and-2.db_info
.....\..\and-2.eco.cdb
.....\..\and-2.eds_overflow
.....\..\and-2.fit.qmsg
.....\..\and-2.fnsim.cdb
.....\..\and-2.fnsim.hdb
.....\..\and-2.fnsim.qmsg
.....\..\and-2.hier_info
.....\..\and-2.hif
.....\..\and-2.map.cdb
.....\..\and-2.map.hdb
.....\..\and-2.map.qmsg
.....\..\and-2.pre_map.cdb
.....\..\and-2.pre_map.hdb
.....\..\and-2.psp
.....\..\and-2.rtlv.hdb
.....\..\and-2.rtlv_sg.cdb
.....\..\and-2.rtlv_sg_swap.cdb
.....\..\and-2.sgdiff.cdb
.....\..\and-2.sgdiff.hdb
.....\..\and-2.signalprobe.cdb
.....\..\and-2.sim.hdb
.....\..\and-2.sim.qmsg
.....\..\and-2.sim.qrpt
.....\..\and-2.sim.rdb
.....\..\and-2.sim.vwf
.....\..\and-2.sld_design_entry.sci
.....\..\and-2.sld_design_entry_dsc.sci
.....\..\and-2.syn_hier_info
.....\..\and-2.tan.qmsg
    

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