Description: dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
- [VerilogGrammarCheckmanual.Rar] - Verilog Grammar Check manual, it would b
- [24miao] - 24 seconds remaining systems (5,250) usi
- [FPGA_27eg] - FPGA value of the 27 examples. Rar inclu
- [dynamic_display] - 4 digital LED dynamic display of the Ver
- [TUSB3410] - TUSB3410 package plans can be used, I us
- [clock] - dp_xiliux the CPLD Verilog design experi
- [EP2C5_EP2C8_V5] - Good to share information and hurricane
- [traffic] - Simulation of traffic lights verilog CPL
- [dem4bit_hienthi] - the verilog source code for being an exa
- [8led] - verilog HDL on the effect of 8-segment L
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