Description: random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
- [随机数生成器] - VC2004
- [8octavevhdl] - the document available VHDL Language 8 c
- [random_number] - Have to obey normal, Rayleigh, Poisson d
- [sin] - Sinusoidal signal generator procedures,
- [DDS] - DDS-based digital phase-shifting sinusoi
- [CPLD_Design_50] - 50 cases of practical CPLD design, very
- [verilog_risc] - RISC state machine consists of three fun
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