LCD_VHDL LCD module output VHDL procedures to achi

Title: LCD_VHDL

Category:
source in ebook
Tags:
[VHDL] [源码]
File Size:
426kb
Update:
2012-11-26
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Uploaded by:
sudy1114

Description: LCD module output VHDL procedures to achieve the function of the procedure is a standard 16 × 2 character LCD module to display the string

Downloaders recently: [More information of uploader sudy1114]

To Search: LCD_VHDL.rar VHDL L lcd vhdl 16

[keyboardScan] - PS2 keyboard scan code interception inte
[ps2_keyboard] - ps2 keyboard verilog source code, to sup
[LCD1602] - LCD1602 display the source code 1. Sourc
[16X2-LCD-FPGA] - 16x2 LCD display driver design of the FP
[DE2_with_VGA_LCM] - altera de2 board vga lcd control quatus
[FlashGISv0] - vb development of GIS electronic map, qu
[LaneMaking1] - Mapped images to the main lines laneMaki
[S9_PS2_LCD] - Keyboard input LCD display module charac
[lcd_driver_4bit] - it is a 4-bit lcd driver written in veri

File list (Check if you may need any files):

S6_LCD_VHDL
...........\Doc
...........\...\程序说明.txt
...........\Proj
...........\....\cmp_state.ini
...........\....\db
...........\....\..\cntr_ea7.tdf
...........\....\..\cntr_ed8.tdf
...........\....\..\cntr_hd8.tdf
...........\....\..\Proj.asm.qmsg
...........\....\..\Proj.asm_labs.ddb
...........\....\..\Proj.cbx.xml
...........\....\..\Proj.cmp.cdb
...........\....\..\Proj.cmp.hdb
...........\....\..\Proj.cmp.logdb
...........\....\..\Proj.cmp.rdb
...........\....\..\Proj.cmp.tdb
...........\....\..\Proj.cmp0.ddb
...........\....\..\Proj.cmp2.ddb
...........\....\..\Proj.db_info
...........\....\..\Proj.eco.cdb
...........\....\..\Proj.fit.qmsg
...........\....\..\Proj.hier_info
...........\....\..\Proj.hif
...........\....\..\Proj.map.cdb
...........\....\..\Proj.map.hdb
...........\....\..\Proj.map.logdb
...........\....\..\Proj.map.qmsg
...........\....\..\Proj.pre_map.cdb
...........\....\..\Proj.pre_map.hdb
...........\....\..\Proj.psp
...........\....\..\Proj.rtlv.hdb
...........\....\..\Proj.rtlv_sg.cdb
...........\....\..\Proj.rtlv_sg_swap.cdb
...........\....\..\Proj.sgdiff.cdb
...........\....\..\Proj.sgdiff.hdb
...........\....\..\Proj.signalprobe.cdb
...........\....\..\Proj.sld_design_entry.sci
...........\....\..\Proj.sld_design_entry_dsc.sci
...........\....\..\Proj.syn_hier_info
...........\....\..\Proj.tan.qmsg
...........\....\..\Proj_cmp.qrpt
...........\....\div16.bsf
...........\....\lcd.bsf
...........\....\LCD_test.bdf
...........\....\lcd_test.bsf
...........\....\LCD_Test.qpf
...........\....\LCD_Test.qws
...........\....\Proj.asm.rpt
...........\....\Proj.cdf
...........\....\Proj.done
...........\....\Proj.fit.eqn
...........\....\Proj.fit.rpt
...........\....\Proj.fit.summary
...........\....\Proj.flow.rpt
...........\....\Proj.map.eqn
...........\....\Proj.map.rpt
...........\....\Proj.map.summary
...........\....\Proj.pin
...........\....\Proj.pof
...........\....\Proj.qsf
...........\....\Proj.sof
...........\....\Proj.tan.rpt
...........\....\Proj.tan.summary
...........\....\Proj_assignment_defaults.qdf
...........\....\Proj_description.txt
...........\Src
...........\...\char_ram.vhd
...........\...\DIV16.v
...........\...\lcd.vhd

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