Description: This my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing.
File list (Check if you may need any files):
dlxpipeline.v
instdecode.v
instexec.v
instfetch.v
memaccess.v
RAM.v
test_dlx.v
wirteback.v
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